1. Field of the Invention
This invention relates to devices and methods to process data from Digital Versatile Disks, or DVD. More particularly, the present invention relates to improved devices and methods for detecting synchronization patterns to enable accurate demodulation of a DVD bitstream.
2. Description of the Related Art
A sector in a DVD is variously called a data sector, a recording sector or a physical sector, depending upon its configuration. FIG. 1 shows a data sector of a DVD disk. As shown in FIG. 1, a data sector includes 2048 bits of data, 4 bytes of identification (ID) data, 2 bytes of ID Error Detection code (IED), 6 bytes of Copyright Management Information (CPR_MAI) and 4 bytes of Error Detection Code (EDC). The 2048 bytes of data are then scrambled, using a feedback shift register. An ECC block is made up of 16 of the data sectors shown in FIG. 1. The 16 data sectors of the ECC block are then encoded, using Cross-Interleaved Reed-Solomon Code (CIRSC). An ECC block, including outer code parity (PO) and inner code parity (PI) is shown in FIG. 2. As shown in FIG. 2, 10 bytes of PI are added after each row, and one row of 182 bytes of PO are added after each of the 16 data sector of the ECC block, for a total of 16 rows of 182 bytes of PO data.
A recording sector is formed by interleaving the PO data in each of the 16 data sectors. One such recording sector is shown in FIG. 3. Each recording sector, therefore, includes a data sector consisting of 12 rows of 172 bites, each row having 10 bytes of PI data appended thereto. One row of 182 bytes of PO data is also included, as a result of the interleaving process referred to above.
Finally, a physical sector, according to the DVD specification, is formed by a two step process. First, an 8:16 modulation conversion is carried out, which effectively doubles the width of each sector. Then, 32 bits of frame synchronization information are prepended to each of the recording sectors in each row. A physical sector is shown in FIG. 4. As shown therein, each sync frame includes 4 bytes of synchronization information, each indicating the start of a recording sector, each recording sector consisting of 1456 bits, or 172 bytes of data and 10 bytes of PI information. Each synchronization code (hereafter xe2x80x9csync patternxe2x80x9d) SYN0 to SYN7 is selected according to sync tables, not shown.
To access (e.g., to read or write) data from a DVD-ROM or DVD-RAM, a DVD read or read/write device must find the beginning of each physical sector. As shown in FIG. 4, only a single SYN0 bit pattern is included in each physical sector. To find the beginning of a physical sector, therefore, requires the DVD device to find the SYN0 bit pattern. To read the data encoded on the disk once the SYN0 pattern has been found, the DVD device must then demodulate the data portions of the recording sectors following the sync patterns SYN0 to SYN7. To demodulate the data portion of a sync frame, therefore, the end of the SYN0 pattern is typically detected, as shown in FIG. 5.
FIG. 5 shows a bit stream including four sync frames starting with SYN0, the beginning of a physical sector. After the SYN0 pattern is found, a SYNC_DETECT signal is typically generated and a bit stream counter is initialized at 32 and started. Whenever the four least significant bits (hereafter xe2x80x9cLSBxe2x80x9d) are zero, a demodulation enable signal DEMOD_EN is generated, thus generating a DEMOD_EN signal every 16 bits. FIG. 6 illustrates the manner in which the DEMOD_EN are generated. The DEMOD_EN signals enable a 16:8 demodulation of the data previously having undergone the 8:16 modulation process referred to relative to FIG. 4. The bit stream counter is re-initialized to 0 after it reaches 1488, and the DEMOD_EN signals are again generated when the counter is between 32 and 1488, thus generating the DEMOD_EN pulses only within the 1456 bits of data within each sync frame of the physical sector while avoiding generating the demodulation signals DEMOD_EN within the sync patterns SYN1 through SYN7. Alternatively, a SYNC_DETECT pulse is generated upon detecting each sync pattern and the counter initialized to 32. The DEMOD_EN pulses are then generated when the bit stream counter is between 32 and 1488. Alternatively still, the bit stream counter may be initialized to zero each time the SYNC_DETECT signal is generated and count between 0 and 1489. The DEMOD_EN pulses are then generated when the counter is between 0 and 1455.
However, these demodulation schemes assume that each and every sync frame has exactly 1488 bits, that each sync pattern is exactly 32 bits in length and that the data portion of each sync frame is exactly 1456 bits in length. When these conditions do not hold, demodulation is no longer possible. For example, if any given sync pattern is not detected because of random noise or because it is corrupted or missing, for example, the bit stream counter will not be properly initialized, and demodulation of the data will be impossible. Also, if the length of the data portion of the sync frame is not exactly equal to 1456 bits, the demodulation enable signals DEMOD_EN will not properly parse the modulated sync frame data and the original 8-bit data will be unrecoverable for that sync frame. Such problems have conventionally rendered demodulation of data encoded on DVDs with corrupted, missing or unreadable sync patterns or sync frame data portions impossible.
Such demodulation schemes suffer from another disadvantage that, although occurring rather infrequently, nevertheless may render demodulation of the input data stream from the DVD impossible. Indeed, there is believed to be an approximately {fraction (1/10)}5 chance that random noise may result in one of the 32 bits read from a sync pattern to be in error, resulting in a mismatch of one of the sync patterns SYN0 to SYN7. Failure to properly detect the sync patterns SYN0 to SYN7 renders demodulation of the encoded data impossible. Sync patterns also may be falsely detected in the data portion of sync frames. Such an erroneous sync pattern detection will conventionally trigger the generation of a SYNC_DETECT pulse, as shown in FIGS. 5 and 6. Upon generation of such an erroneous SYNC_DETECT signal, the bit stream counter will be initialized, and the DEMOD_EN signals will be incorrectly generated through the next sync pattern, again rendering the demodulation of the encoded data impossible.
What are needed, therefore, are devices and methods of generating demodulating pulses for DVD data input bitstreams that are tolerant of missing and/or corrupted sync patterns and/or sync frame data portions of non-standard length. What are also needed are devices and methods for detecting sync pulses and facilitating demodulation of DVD data that are not affected by the sync pattern detection problems associated with conventional devices and methods.
The present invention, therefore, provides devices and methods for generating demodulating pulses for DVD data input bitstream that are tolerant of missing and/or corrupted sync patterns and/or sync frame data of non-standard length. The present invention also provides devices and methods for detecting sync pulses to enable accurate demodulation of DVD bitstream that are not affected by the sync pattern detection problems associated with conventional devices and methods.
In accordance with the principles of the invention above and those that will be mentioned and will become apparent below, a method of processing a DVD bitstream, according to an embodiment of the present invention, comprises the steps of:
reading the DVD bitstream, the bitstream including a sync frame;
creating a sync window, the sync window being open at least during an expected timing of a sync detection signal within the sync frame;
detecting the sync pattern within the sync frame; and
generating the sync detection signal only when the sync pattern has been detected and the sync window is open.
According to further embodiments, in single-bit mode, the sync window may be open 2 bits before the expected timing of the sync detection signal and 2 bits after the generation of the sync detection signal. In dual bit mode, the sync window may be open 1 bit before the expected timing of the sync detection signal and 1 bit after the generation of the sync detection signal. In quad-bit mode, the sync window may be open only during the expected timing of the sync detection signal. A step of outputting a demodulation enable signal every 16 bits after generation of the sync detection signal until a sync frame boundary is encountered may also be carried out. A step of counting read channel bits of the DVD bitstream in a counter may also be carried out, as well as a step of resetting the counter upon generation of the sync detection signal and upon reaching the sync frame boundary. The resetting step preferably resets the counter to a value that accounts for a timing difference between the expected timing of the sync detection signal and a timing of the generation of the sync detection signal. A step of generating a pseudo sync detection signal after the sync window closes when no sync detection signal is generated during a time when the sync window is open may also be carried out.
The present invention may also be viewed as a DVD sync pattern detection circuit which, in one embodiment, comprises:
a sync window generator to generate a sync window signal;
a sync pattern detector, the sync pattern detector generating a sync detection signal only when both a sync pattern is detected in a DVD input stream and the sync window signal is asserted; and
a read channel bit counter, the read channel bit counter generating a read counter signal to control the sync window generator and being reset when the sync pattern detector detects the sync pattern.
According to other embodiments, the sync window generator may further comprise means for generating a pseudo-sync signal, the pseudo-sync signal being generated when the sync pattern detector fails to detect a sync pattern when the sync window signal is asserted. A logic circuit coupled to the sync pattern detector and to the sync window generator may also be included, the logic circuit outputting a sync signal upon assertion of one of the pseudo-sync signal and the sync detection signal. The logic circuit may include an OR logic circuit. The read channel bit counter may include an 11-bit counter. The read channel bit counter may generate a demodulation enable signal during a data portion of a sync frame when a four least significant bits of the read channel bit counter are zero. The read counter signal preferably controls the width of the sync window signal. In single-bit mode, the sync window signal is preferably asserted 2 bits before the expected timing of the sync detection signal and de-asserted 2 bits after the generation of the sync detection signal. In dual-bit mode, the sync window signal is preferably asserted 1 bit before the expected timing of the sync detection signal and de-asserted 1 bit after the generation of the sync detection signal. In quad-bit mode, the sync window signal is preferably asserted only during the expected timing the sync detection signal.
The present invention, according to another embodiment thereof, is also a DVD controller, comprising:
means for reading a DVD bitstream;
means for generating a sync window signal;
means for detecting a sync pattern within the DVD bitstream, the sync pattern detecting means generating a sync detection signal only when both the sync pattern is detected and the sync window signal is asserted; and
means for counting channel bits, the channel bit counting means generating a read counter signal to control the sync window generating means and resetting when the sync pattern detecting means detects the sync pattern.
According to still further embodiments, the sync window signal generating means may further comprise means for generating a pseudo-sync signal, the pseudo-sync signal being generated when the sync pattern detecting means fails to detect a sync pattern when the sync window signal is asserted. A logic circuit may be coupled to the sync pattern detecting means and to the sync window signal generating means, the logic circuit outputting a sync signal upon assertion of one of the pseudo-sync signal and the sync detection signal. The channel bit counting means may include means for generating a demodulation enable signal during a data portion of a sync frame when the four least significant bits of the read channel bit counting means are zero. The read counter signal preferably controls the width of the sync window signal. In single-bit mode, the sync window signal generating means preferably asserts the sync window signal 2 bits before the expected timing of the sync detection signal and de-asserts the sync window signal 2 bits after the generation of the sync detection signal. In dual-bit mode, the sync window signal generating means preferably asserts the sync window signal 1 bit before the expected timing of the sync detection signal and de-asserts the sync window signal 1 bit after the generation of the sync detection signal. In quad-bit mode, the sync window signal generating means preferably asserts the sync window only during an expected timing the sync detection signal.
The present invention may also be viewed as a DVD bitstream processing circuit, comprising:
a sync window signal generator;
a sync pattern detector to detect a sync pattern within a DVD bitstream, the sync pattern detector generating a sync detection signal only when both the sync pattern is detected and a sync window signal is asserted; and
a channel bit counter, the channel bit counter generating a read counter signal to control the sync window signal generator and resetting when the sync pattern detector detects the sync pattern.
According to other embodiments, the sync window signal generator may further generate a pseudo-sync signal, the pseudo-sync signal being generated when the sync pattern detector fails to detect a sync pattern when the sync window signal is asserted. A logic circuit may also be coupled to the sync pattern detector and to the sync window signal generator, the logic circuit outputting a sync signal upon assertion of either the pseudo-sync signal or the sync detection signal. The channel bit counter may generate a demodulation enable signal during a data portion of a sync frame when the four least significant bits of the read channel bit counter are zero. The read counter signal may control the width of the sync window signal and, in single-bit mode, the sync window signal generator may assert the sync window signal 2 bits before the expected timing of the sync detection signal and de-assert the sync window signal 2 bits after the generation of the sync detection signal. The read counter signal may control the width of the sync window signal and, in dual-bit mode, the sync window signal generator may assert the sync window signal 1 bit before an expected timing of the sync detection signal and de-assert the sync window signal 1 bit after the generation of the sync detection signal. In quad-bit mode, the sync window signal generator may assert the sync window only during the expected timing the sync detection signal.